The present invention relates to IC test equipment of the type that supplies a test pattern to an IC under test and compares its operating current with a reference one.
Conventional IC test equipment of this kind perform the test by applying a test pattern to the IC under test and checking whether or not a mean value of its power supply current dissipated over tens of its operating cycles is greater than a predetermined value. According to the IC under test, however, the operating power supply current may sometimes vary within one operation cycle. For example, when a logic circuitry IC, which operates on a plurality of logic signals, goes to logic "1" state at its many parts in one cycle, a large current flows, but in another cycle in which it goes to logic "0" state at many parts, the current flow is small; thus, the power supply current varies for each cycle. Also in a memory IC, when it is addressed, the power supply current increases temporarily and the current flow differs with the state in which the IC is addressed. In the case of a C-MOS IC, when it goes from logic "1" state to logic "0" state or vice versa, a pair of FETs which perform a complementary operation are both turned ON instantaneously, causing a pulsewise increase in the power supply current.
As mentioned above, various semiconductor integrated circuits may sometimes be subject to variations in the power supply current within one operation cycle and this often affects the characteristics of the IC under test.
As referred to above, however, there has not been conducted a test for checking whether or not current dissipated for a certain period in each operation cycle is within a predetermined value. One possible technique for such a test based on the prior art is as follows: As shown in FIG. 1, a test pattern is supplied from a test pattern generator 21 to an IC under test 22, which operates with the cycle of the test pattern. The IC under test 22 is also supplied with its operating power from a power source terminal 23. For detecting the operating power, a current detecting resistor 24 of a small resistance value is connected between the power source terminal 23 and a power source terminal of the IC under test 22, and the resistor 24 is connected at both ends to a voltage-current converter 25. Across the resistor 24 is induced a voltage which is proportional to the instantaneous value of a current Io flowing from the power source terminal 23 to the IC under test 22, and the instantaneous value of the voltage is converted to a current Ix. Accordingly, the current Ix corresponds to the instantaneous operating current Io of the IC under test 22. The current Ix is charged in a capacitor 12 via a switch 11. The capacitor 12 is temporarily shorted via a switch 13 at the start of each operation cycle so that charges stored in the capacitor 12 are discharged therefrom, presetting it to zero potential. The switch 11 is held in the ON state in a predetermined phase for a predetermined period in each operation cycle. In consequence, charges corresponding to an integrated value of the current Io which flows into the IC under test 22 from the power source terminal 23 during the ON state of the switch 11 is stored in the capacitor 12. The voltage of the capacitor 12 is compared by a comparator 15 with a reference voltage Er of a reference voltage source 14. When the voltage of the capacitor 12 exceeds the reference voltage Er, the output of the comparator 15 goes high, whereas when the voltage of the capacitor 12 is lower than the reference voltage Er, the output of the comparator 15 remains low. The output of the comparator 15 is input by a strobe pulse into a D flip-flop 34 after turning-OFF of the switch 11 but before turning-ON of the switch 13. If the output of the flip-flop 34 is high-level, then it is displayed, for instance, on a display (not shown), that the IC under test is defective. In the alternative, the output of the flip-flop 34 is stored in a memory for each operation cycle for an analysis of defectives. The test pattern generator 21 supplies a control circuit 16 with a clock synchronized with the start of each operation cycle, and the control circuit 16 creates control signals for the switches 11 and 13 and the strobe pulse for the flip-flop 34.
With such an arrangement, it can be checked whether or not current dissipated in a specified period of each operation cycle exceeds a reference value. But this arrangement cannot make a correct test unless the capacitor 12 is highly precise and stable in its capacitance value. Such a high-precision, high-stability capacitor is extremely expensive. Furthermore, if the comparator 15 has an offset voltage, since the sum of the offset voltage and the reference voltage Er is compared with the voltage of the capacitor 12, the comparator 12 will provide an inaccurate comparison result correspondingly.